- 郑旭强
- 副研究员
简 历：
于2006年、2009年和2018年分别从中南大学获本科、硕士和英国林肯大学获博士学位；于2018年7月加入中国科学院微电子研究所高频高压中心任副研究员。
长期从事超高速串行接口和超高速数据转换器的研究工作，先后在国际知名期刊和会议发表论文40多篇。担任JSSC和TCAS-I的评审。他的研究方向主要包括高速串行通信接口、高速数据模拟转化器和高速低抖动时钟发生器。
社会任职： 研究方向：超高速串行接口和超高速数据转换器的研究 承担科研项目情况：
2010年至2015年在清华大学微纳电子系从事高速串行接口芯片及高速模拟数字转换器芯片的研发，参与完成了“核高基”项目“多通道10Gb/s IP核设计”、“863”项目“40Gb/s高速串行接口IP核设计”和“深圳知识创新计划”项目“14bit 250MS/s流水线ADC设计”；2015年至2018年参与了欧盟FP7项目EYE2E (269118)、 LIVCODE (295151)和欧盟地平线2020项目STEP2DYNA (691154)等项目。
代表论著：
[1] X. Zheng, C. Zhang, and F. Lv et al., “A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 52, no. 11, pp. 2963-2978, Nov. 2017.
[2] X. Zheng, Z. Wang, and F. Li et al., “A 14-bit 250 MS/s IF sampling pipelined ADC in 180 nm CMOS process,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 63, no. 9, pp. 1381-1392, Sep. 2016.
[3] S. Yuan, L. Wu, Z. Wang, and X. Zheng et al., “A 70 mW 25 Gb/s quarter-rate SerDes transmitter and receiver chipset with 40 dB of equalization in 65 nm CMOS technology,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 63, no. 7, pp. 939-949, Jul. 2016.
[4] K. Huang, Z. Wang, and X. Zheng et al., “A 80 mW 40 Gb/s transmitter with automatic serializing time window search and 2-tap pre-emphasis in 65 nm CMOS technology,” IEEE Trans. Circuits Syst. I, Reg. Papers (TCAS-I), vol. 62, no. 5, pp. 1441-1450, Apr. 2015.
[5] S. Yuan, Z. Wang, and X. Zheng et al., “A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-lane source-synchronous transmitter in 65-nm bulk CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs (TCAS-II), vol. 61, no. 4, pp. 209-213, Apr. 2014.
[6] X. Zheng, C. Zhang, and F. Lv et al.,“A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Apr. 2017.
[7] X. Zheng, F. Lv, and F. Zhao et al.,“A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Apr. 2017.
[8] S. Yuan, L. Wu, Z. Wang, and X. Zheng et al., “A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2015, pp.1-4.
[9] K. Huang, D. Luo, Z. Wang, and X. Zheng et al., “A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2015, pp. 1-4.
[10] K. Huang, Z. Wang, and X. Zheng et al., “A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2014, pp. 1-4.
[11] X. Zheng, C. Zhang, and F. Lv et al., “A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), Sep. 2016, pp. 305-308.
[12] S. Yuan, L. Wu, Z. Wang, and X. Zheng et al., “A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS,” in Proc. IEEE European Solid-State Circuits Conf. (ESSCIRC), Nov. 2015, pp. 144-147.
X. Zheng, C. Zhang, and S. Yuan et al., “An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2016, pp. 85-88.
专利申请： 获奖及荣誉：
