[TC] Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks, by Wenyan Lu, Guihai Yan, Jiajun Li, Xiaowei Li, Accepted by IEEE Transactions on Computers. [TCAD] ShuttleNoC: Power-adaptable Communication Infrastructure for Many-core Processors, by Hang Lu; Yisong Chang; Guihai Yan; Ning Lin; Xin Wei; Xiaowei Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Early Access ), 12 July 2018. [HPCA] FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks, by Wenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li, In proceedings of 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), Austin, USA, 4-8 Feb. 2017 [TC] CoreRank: Redeeming 'Sick Silicon' by Dynamically Quantifying Core-level Healthy Condition, by Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, IEEE Transactions on Computers, Volume: 65, Issue: 3, pp.716 - 729, March 1 2016 [TPDS] EcoUp: Towards Economical Datacenter Upgrading, by Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li IEEE Transactions on Parallel and Distributed Systems, Volume: 27, Issue: 7, pp. 1968-1981, July 1 2016 [TC] An Analytical Framework for Estimating Scale-out and Scale-up Power Efficiency of Heterogeneous Manycores, by Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li IEEE Transactions on Computers, Volume: 65, Issue: 2, pp. 367-381, Feb. 1 2016 [DAC] RISO: Relaxed Network-on-Chip Isolation for Cloud Processors, by Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li, In the Proceedings of Design Automation Conference (DAC2013), Austin, Texas, USA, June 2-6, 2013. [HPCA] AgileRegulator: A Hybrid Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture, by Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang, In the Proceedings of High-Performance Computer Architecture Symposium 2012 (HPCA2012), New Orleans, Louisiana, pp.287-298, Feb. 25-29, 2012. [TC] ReviveNet: A Self-adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation, by Guihai Yan, Yinhe Han, Xiaowei Li, IEEE Transactions on Computers (TC), Vol.60, No.9, pp.1219-1232, Sep. 2011. [ISCA] Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors, by Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li, In the Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA'10), Saint-Malo, France. pp.485-496, Jun. 2010.
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